The present invention relates generally to data transmitting buses in a data processing system, and more particularly to an assist circuit for supplying current to conductors in a data transfer bus for assisting changes in the states of the conductors in the bus.
Data processing systems contain data transfer buses such as, for instance, a data bus between a processor and a memory. The data processing system is typically timed by a clock circuit which controls the processor and the memory, allowing the processor to place data on the bus, and giving sufficient time for the data signals to stabilize before the memory reads the data from the bus for storage.
Assist circuits are known which, at or near the beginning of the processor to memory cycle, supply current to each conductor in the data bus to quickly set each conductor in the data bus to its inactive state. By use of such assist circuits, the processor does not need to supply all of the current to return the conductors in the data bus to their inactive states, but needs only to change selected conductors in the data bus to their active states which correspond to data to be transferred. However, if the prior known bus assist circuits are attempting to change the state of a conductor to its inactive state at or near the same time the processor is attempting to change the state of that same conductor to its active state, the time needed to stabilize the voltage level or state on that conductor will be lengthened.
It will be readily understood by those skilled in the art that, while the example used herein is for a data bus between a processor and a memory where the processor is controlling the state on the conductors of a data bus, the present invention is equally useful in a memory bus wherein the memory is controlling the state of the conductors on the bus, or between a processor and a peripheral device, or in a data bus between individual peripheral devices.